This invention relates in general to semiconductor manufacturing and, more particularly, to a method and apparatus for reducing loading effects on a semiconductor manufacturing component during an etch process.
Advances in integrated circuit (IC) design and the manufacturing techniques used to create ICs have contributed to the reduction in size of design features that form ICs. As the feature size shrinks, the number of features that may be placed in an IC increases. The features are typically formed on a semiconductor wafer by imaging patterns from a photomask into a resist layer, developing and etching the resist layer to expose the appropriate parts of a conductive layer, such as polysilicon or metal, and etching the conductive layer to form desired patterns in the conductive layer.
The etching step may be performed by a plasma etching reactor with endpoint detection. The endpoint is typically determined by a dedicated hardware and/or software system connected to the process chamber by an optical fiber. During the etch process, the material to be etched reacts with the plasma and the optical fiber collects a photo emission intensity signal of the plasma. The intensity of the signal is generally proportional to the etch rate and the process time is proportional to the total amount of material to be etched. Currently, a test wafer may be run through a semiconductor manufacturing process to determine if the endpoint of the etch process is correct. If the features on the test wafer show under or over-etch, the endpoint is adjusted and the process is repeated until an appropriate endpoint is determined for the etch process.
In accordance with the teachings of the present invention, disadvantages and problems associated with reducing loading effects on a semiconductor manufacturing component during an etch process have been substantially reduced or eliminated. In a particular embodiment, a method for reducing loading effects on a semiconductor manufacturing component during an etch process is disclosed that adjusts the etch process based on a transmittance associated with a photomask.
In accordance with one embodiment of the present invention, a method for reducing loading effects on a semiconductor manufacturing component during an etch process includes calculating a transmittance associated with a photomask and adjusting an etch process for a material formed on a semiconductor manufacturing component based on the transmittance calculated for the photomask.
In accordance with another embodiment of the present invention, a method for reducing loading effects on a semiconductor component during a plasma etch process includes determining a maximum acceptable difference between a first clear area percentage and a second clear area percentage for a plasma etch process and calculating a transmittance difference between a first transmittance for a first feature associated with a photomask and a second transmittance for a second feature associated with the photomask. The plasma etch process for a material formed on a semiconductor manufacturing component is adjusted if the transmittance difference exceeds the maximum acceptable difference for the plasma etch process.
In accordance with a further embodiment of the present invention, a method for manufacturing a photomask includes calculating a transmittance associated with a mask pattern file. A pattern from the mask pattern file is imaged into a resist layer formed on a photomask blank and the resist layer is developed to expose portions of a conductive layer disposed on a transparent substrate. An etch process for the photomask blank is adjusted based on the transmittance associated with the mask pattern file and the etch process is used to etch the conductive layer and expose portions of the transparent substrate.
Important technical advantages of certain embodiments of the present invention include the ability to characterize transmittance properties of a photomask based on a mask pattern file. A photomask is typically manufactured by exposing features from a mask pattern file, generated by a chip designer, into resist layer of a photomask blank. A photomask manufacturer may analyze the mask pattern file to determine if the features will create loading effects during an etch process. If the pattern formed by the features in the mask pattern file will cause loading effects to occur during an etch process, extra features may be added to the mask pattern file to reduce or even eliminate the loading effects.
Another important technical advantage of certain embodiments of the present invention includes the ability to accurately determine the endpoint of an etch process by calculating the transmittance associated with a photomask. Etching rates for materials typically formed on a semiconductor wafer are a function of the exposed area on a surface to be etched and the exposed area is directly related to the transmittance associated with a photomask. Due to the relationship between the transmittance and the exposed area, the etch rate of a material may be affected by the transmittance of the photomask used to image a pattern into the material. In order to reduce or eliminate loading effects during the etch process, the transmittance associated with the photomask can be used to determine the endpoint of the etch process.